MSM6636B

OKI - SAE-J1850 Multiplex Communication Protocol Conformity Transmission Controller

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Price:: US $4.80~6.00 / piece [Get Latest Price]

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	US $4.80~6.00

PartNumber:: MSM6636B

Brand:: OKI electronic componets - OKI | Pack: SOP | D/C: 06+

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Products Upload time: 2012-08-24

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Part Number:MSM6636B
US $4.80 - 6.00
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Product Summary

GENERAL DESCRIPTION:The MSM6636B is a transmission controller for automotive LAN based on data communication protocol SAE-J1850. This device can realize a data bus topology bus LAN system with a PWM bit encoding method (41.6 kbps) . In addition to a protocol control circuit, MSM6636B has an enclosed quartz oscillation circuit, host CPU interface (parallel interface) , a transmit/receive buffer, and a bus receiver circuit that decreases the burden on the host CPU.

Parametrics

MSM6636B absolute maximum ratings: (1) power supply voitage: DVdd, AVdd -0.3 to + 7.0 V; (2) input voltage: V1 AVdd=DVdd -0.3 to DVDD +0.3 V; (3) output voltage: V0 AVdd=DVdd -0.3 to DVDD +0.3 V; (4) power dissipation Pd (sop)*1 Ta=25°C: 780mW; (5) Storage Temperature Tstg: -55 to +150°C.

Features

MSM6636B features: (1) Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued August 12, 1991) ; (2) Non-destructive collision and priority control using CSMA/CD; (3) Internal transmit buffer (1 frame) and receive buffer (2 frames) ; (4) Modulating/demodulating: PWM (Pulse Width Modulation) ; (5) Transmission speed: 41.6 kbps; (6) Multi-address setting with physical addressing: 1 type/functional addressing: 15 types; (7) Address filter function by multi-addressing (broadcasting possible) ; (8) Automatic retransmission function by arbitration loss and non ACK; (9) Three types of in-frame response support; (10) Error detection by cyclic redundancy check (CRC) ; (11) Various communication error detections; (12) Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function; (13) Host CPU interface is accessed in parallel; (14) Sleep function: low current consumption mode by oscillation stop (IDS Max<50μA) SLEEP/WAKE UP control from host CPU, WAKE UP via LAN bus.