LPC1758FBD80

Product Summary

The LPC1758FBD80 ARM Cortex-M3 based microcontroller or embedded applications featuring a high level of integration and low power consumption. The LPC1758FBD80 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. Applications of the LPC1758FBD80 include: eMetering, Lighting, Industrial networking, Alarm systems, White goods and Motor control.

Parametrics

LPC1758FBD80 limited ratings: (1) supply voltage (3.3 V) VDD: 2.4V, 3.6V (core and external rail) ; (2) regulator supply voltage (3.3 V) VDD: 2.4V, 3.6V; (3) analog 3.3 V pad supply voltage VDDA: -0.5V to 4.6V; (4) input voltage on pin VBAT VI(VBAT) : -0.5V to 4.6V (for the RTC) ; (5) input voltage on pin VREFP VI (VREFP) : -0.5V to 4.6V; (6) supply current IDO: 100mA; (7) ground current ISS: 100mA; (8) storage temperature Tstg: -65°C to +150°C.

Features

LPC1758FBD80 features: (1) ARM Cortex-M3 processor, running at frequencies of up to 100 MHz supporting eight regions is included;(2) ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC) ; (3) Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states; (4) In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software; (5) On-chip SRAM includes; (6) Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access; (7) Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet (LPC1758 only) , USB, and DMA memory, as well as for general purpose CPU instruction and data storage; (8) Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers; (9) Multilayer AHB matrix interconnect provides a separate bus for each AHB master.AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only) , and the USB interface. This interconnect provides communication with no arbtration delays; (10) Split APB bus allows high throughput with few stalls between the CPU and DMA; (11) Serial interfaces;(12) On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller; (13) USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only; (14) Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support; (15) CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels; (16) SPI controller with synchronous, serial, full duplex communication and programmable data length; (17) Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller; (18) Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode; (19) On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output; (20)Other peripherals; (21) 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller; (22) 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.

Diagrams